View SMJ28F010B_1026943.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SMJ28F010B 131072 BY 8-BIT FLASH MEMORY
SGMS738 - APRIL 1998
D D D D D D D D D D
D
Organization . . . 131 072 x 8-Bit Flash Memory Pin Compatible With Existing 1M-bit EPROMs High-Reliability MIL-PRF-38535 Processing VCC Tolerance 10% All Inputs / Outputs TTL Compatible Maximum Access / Minimum Cycle Time 28F010B-12 120 ns '28F010B-15 150 ns '28F010B-20 200 ns Industry-Standard Programming Algorithm 10 000 Program / Erase-Cycle Latchup Immunity of 250 mA on All Input and Output Lines Low Power Dissipation ( VCC = 5.5 V ) -Active Write . . . 55 mW -Active Read . . . 165 mW -Electrical Erase . . . 82.5 mW -Standby . . . 0.55 mW (CMOS-Input Levels) Military Temperature Range - 55C to 125C
JDD or FE PACKAGE ( TOP VIEW )
VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC W NC A14 A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
PIN NOMENCLATURE A0 - A16 DQ0 - DQ7 E G NC VCC VPP VSS W Address Inputs Inputs (programming) / Outputs Chip Enable Output Enable No Internal Connection 5-V Power Supply 12-V Power Supply Ground Write Enable
description
The SMJ28F010B is a 104 8 576-bit, programmable read-only memory that can be electrically bulk-erased and reprogrammed. It is available in 10 000 program / erase-endurance-cycle version. The SMJ28F010B flash memory is offered in a 32-lead ceramic 600-mil side-braze dual in-line package (DIP) (JDD suffix) and a leadless ceramic chip carrier (FE suffix).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 1998, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
1
SMJ28F010B 131072 BY 8-BIT FLASH MEMORY
SGMS738 - APRIL 1998
device symbol nomenclature
SMJ28F010B -12 JDD M
Temperature Range Designator M = - 55C to 125C
Package Designator JDD = Ceramic Side-Braze Dual- In-Line Package
Speed Designator -12 = 120 ns -15 = 150 ns -20 = 200 ns
2
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
SMJ28F010B 131072 BY 8-BIT FLASH MEMORY
SGMS738 - APRIL 1998
logic symbol
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 E G W 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22 24 31 0 FLASH MEMORY 131 072 x 8
A
0 131 071
16 G1 [PWR DWN] G2 1, 2 EN (READ) 1C3 (WRITE) A, 3D 4
DQ0
13
A, Z4
DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
14 15 17 18 19 20 21
This symbol is in accordance with ANSI / IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the JDD package.
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
3
SMJ28F010B 131072 BY 8-BIT FLASH MEMORY
SGMS738 - APRIL 1998
functional block diagram
DQ0 - DQ7 8 VPP W State Control To Array Program / Erase Stop Timer Program-Voltage Switch STB E G Chip-Enable and Output-Enable Logic Data Latch Erase-Voltage Switch Input / Output Buffers
Command Register
STB A d d r e s s L a t c h Column Decoder Column Gating
A0 - A16
17
Row Decoder
1 048 576-Bit Array Matrix
4
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
SMJ28F010B 131072 BY 8-BIT FLASH MEMORY
SGMS738 - APRIL 1998
operation
Table 1 lists the modes of operation for the device. Table 1. Operation Modes
FUNCTION MODE Read Output Disable Read Standby and Write Inhibit g Algorithm-Selection Mode Read Read / Write Output Disable Standby and Write Inhibit Write VPP (1) VPPL VPPL VPPL VPPL VPPH VPPH VPPH VPPH E (22) VIL VIL VIH VIL VIL VIL VIH VIL G (24) VIL VIH X VIL VIL VIH X VIH A0 (12) X X X VIL VIH X X X X A9 (26) X X X VID X X X X W (31) VIH VIH X VIH VIH VIH X DQ0 - DQ7 (13 - 15, 17 - 21) Data Out Hi-Z Hi-Z Manufacturer-Equivalent Code 89h Device-Equivalent Code B4h Data Out Hi-Z Hi-Z Data In
VIL X can be VIL or VIH. VPPL VCC + 2 V; VPPH is the programming voltage specified for the device. For more details, see the recommended operating conditions.
read/ output disable When the outputs of two or more SMJ28F010B devices are connected in parallel on the same bus, the output of any particular device in the circuit can be read with no interference from the competing outputs of other devices. Reading the output of the SMJ28F010B is enabled when a low-level signal is applied to the E and G pins. All other devices in the circuit must have their outputs disabled by applying a high-level signal to one of these pins. standby and write inhibit Active ICC current can be reduced from 30 mA to 1 mA by applying a high TTL level on E or to 100 A with a high CMOS level on E. In this mode, all outputs are in the high-impedance state. The SMJ28F010B draws active current when it is deselected during programming, erasure, or program / erase verification. It continues to draw active current until the operation is terminated. algorithm-selection mode The algorithm-selection mode provides access to a binary code identifying the correct programming and erase algorithms. This mode is activated when A9 ( pin 26) is forced to VID. Two identifier bytes are accessed by toggling A0. All other addresses must be held low. A0 low selects the manufacturer-equivalent code 89h, and A0 high selects the device-equivalent code B4h, as shown in Table 2. Table 2. Algorithm-Selection Modes
IDENTIFIER Manufacturer-Equivalent Code PINS A0 DQ7 DQ6 DQ5 DQ4 0 1 DQ3 1 0 DQ2 0 1 DQ1 0 0 DQ0 1 0 HEX 89 B4
VIL 1 0 0 Device-Equivalent Code VIH 1 0 1 E =VIL, G = VIL, A1 - A8 = VIL, A9 = VID, A10 - A16 = VIL, VPP = VPPL.
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
5
SMJ28F010B 131072 BY 8-BIT FLASH MEMORY
SGMS738 - APRIL 1998
programming and erasure In the erased state, all bits are at a logic 1. Before erasing the device, all memory bits must be programmed to a logic 0. Then the entire chip is erased. At this point, the bits, which are now logic 1s, can be programmed accordingly. See the fast-write and fast-erase algorithms for further details. command register The command register controls the program and erase functions of the SMJ28F010B. The algorithm-selection mode can be activated using the command register in addition to the previously described method. When VPP is high, the contents of the command register and the function being performed can be changed. The command register is written to when E is low and W is pulsed low. The address is latched on the leading edge of the pulse, while the data is latched on the trailing edge. Accidental programming or erasure is minimized because two commands must be executed to invoke either operation. The command register is inhibited when VCC is below the erase / write lockout voltage, VLKO . power-supply considerations Each device must have a 0.1-F ceramic capacitor connected between VCC and VSS to suppress circuit noise. Changes in current drain on VPP require it to have a bypass capacitor as well. Printed-circuit traces for both power supplies should be appropriate to handle the current demand.
command definitions
The commands include read, algorithm-selection mode, set-up-erase, erase, erase-verify, set-up-program, program, program-verify, and reset. Table 3 lists the command definitions with the required bus cycles. Table 3. Command Definitions
COMMAND Read Algorithm-Selection Mode Set-Up-Erase / Erase Erase-Verify Set-Up-Program / Program Program-Verify Reset REQUIRED BUS CYCLES 1 3 2 2 2 2 2 FIRST BUS CYCLE OPERATION Write Write Write Write Write Write Write ADDRESS X X X EA X X X DATA 00h 90h 20h A0h 40h C0h FFh SECOND BUS CYCLE OPERATION Read Read Write Read Write Read Write ADDRESS RA 0000h 0001h X X PA X X DATA RD 89h B4h 20h EVD PD PVD FFh
Legend: EA Address of memory location to be read during erase verify RA Address of memory location to be read PA Address of memory location to be programmed. Address is latched on the falling edge of W. RD Data read from location RA during the read operation EVD Data read from location EA during erase verify PD Data to be programmed at location PA. Data is latched on the rising edge of W. PVD Data read from location PA during program verify Modes of operation are defined in Table 1.
read command Memory contents can be accessed while VPP is high or low. When VPP is high, writing 00h into the command register invokes the read operation. When the device is powered up, the default contents of the command register are 00h and the read operation is enabled. The read operation remains enabled until a different command is written to the command register.
6
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
SMJ28F010B 131072 BY 8-BIT FLASH MEMORY
SGMS738 - APRIL 1998
algorithm-selection mode command The algorithm-selection mode is activated by writing 90h into the command register. The device-equivalent code ( B4h) is identified by the value read from address location 0001h, and the manufacturer-equivalent code ( 89h) is identified by the value read from address location 0000h. set-up-erase / erase commands The erase-algorithm initiates with E = VIL, W = VIL, G = VIH, VPP = VPPH, and VCC = 5 V. To enter the erase mode, write the set-up-erase command, 20h, into the command register. After the SMJ28F010B is in the erase mode, writing a second erase command, 20h, into the command register invokes the erase operation. The erase operation begins on the rising edge of W and ends on the rising edge of the next W. The erase operation requires at least 9.5 ms to complete before the erase-verify command, A0h, can be loaded. Maximum erase timing is controlled by the internal stop timer. When the stop timer terminates the erase operation, the device enters an inactive state and remains inactive until a command is received. program-verify command The SMJ28F010B can be programmed sequentially or randomly, because it is programmed one byte at a time. Each byte must be verified after it is programmed. The program-verify operation prepares the device to verify the most recently programmed byte. To invoke the program-verify operation, C0h must be written into the command register. The program-verify operation ends on the rising edge of W. While verifying a byte, the SMJ28F010B applies an internal margin voltage to the designated byte. If the true data and programmed data match, programming continues to the next designated byte location; otherwise, the byte must be reprogrammed. Figure 1 shows how commands and bus operations are combined for byte programming. erase-verify command All bytes must be verified following an erase operation. After the erase operation is complete, an erased byte can be verified by writing the erase-verify command, A0h, into the command register. This command causes the device to exit the erase mode on the rising edge of W. The address of the byte to be verified is latched on the falling edge of W. The erase-verify operation remains enabled until a command is written to the command register. To determine whether all the bytes have been erased, the SMJ28F010B applies a margin voltage to each byte. If FFh is read from the byte, all bits in the designated byte have been erased. The erase-verify operation continues until all of the bytes have been verified. If FFh is not read from a byte, an additional erase operation needs to be executed. Figure 2 shows the combination of commands and bus operations for electrically erasing the SMJ28F010B. set-up-program / program commands The programming algorithm initiates with E = VIL, W = VIL, G = VIH, VPP = VPPH, and VCC = 5 V. To enter the programming mode, write the set-up-program command, 40h, into the command register. The programming operation is invoked by the next write-enable pulse. Addresses are latched internally on the falling edge of W, and data is latched internally on the rising edge of W. The programming operation begins on the rising edge of W and ends on the rising edge of the next W pulse. The program operation requires 10 s for completion before the program-verify command, C0h, can be loaded. Maximum program timing is controlled by the internal stop timer. When the stop timer terminates the program operation, the device enters an inactive state and remains inactive until a command is received. reset command To reset the SMJ28F010B after set-up-erase-command or set-up-program-command operations without changing the contents in memory, perofrm two consecutive writes of FFh into the command register. After executing the reset command, the device defaults to the read mode.
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
7
SMJ28F010B 131072 BY 8-BIT FLASH MEMORY
SGMS738 - APRIL 1998
fast-write algorithm
Figure 1 shows the process flow for programming the SMJ28F010B. The fast-write algorithm programs in a nominal time of two seconds.
fast-erase algorithm
Figure 2 shows the process flow for erasing the SMJ28F010B using the fast-erase algorithm. The memory array must be completely programmed (using the fast-write algorithm) before erasure begins. Erasure typically occurs in one second.
parallel erasure
Several devices can be erased in parallel, reducing total erase time. Since the rate at which each flash memory can erase differs, every device must be verified separately after each erase pulse. After a given device has been successfully erased, the erase command should not be reissued to this device. All devices that complete erasure should be masked until the parallel erasure process is finished (see Figure 3). Examples of how to mask a device during parallel erase include driving the E pin high, writing the read command (00h) to the device when the others receive a set-up-erase or erase command, and disconnecting the device from all electrical signals with relays or other types of switches.
flow charts
Figure 1, Figure 2, and Figure 3 are flow charts showing the fast-write algorithm, the fast-erase algorithm, and the parallel-erase flow.
8
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
SMJ28F010B 131072 BY 8-BIT FLASH MEMORY
SGMS738 - APRIL 1998
flow charts (continued)
Bus Operation
Start Address = 00h VCC = 5 V 10%, VPP = 12 V 5% Setup X=1
Command
Comments
Initialize Address Standby
Wait for VPP to ramp to VPPH (see Note A) Initialize pulse count
Write Set-Up-Program Command
Write
Write Data Increment Address Wait = 10 s Write Program-Verify Command X=X+1
Set-UpProgram Write Write Data
Data = 40h
Write Standby
Wait = 6 s No Read Fail and Verify Byte
Valid address / data Wait = 10 s
Write
ProgramVerify
Data = C0h; ends program operation Wait = 6 s
X = 25?
Standby
Yes
Pass Interactive Mode No Last Address ?
Read
Read byte to verify programming; compare output to expected output
--
Yes Write Read Command Power Down Apply VPPL Apply VPPL
--
--
Write
Read
Data = 00h; resets register for read operations Wait for VPP to ramp to VPPL (see Note B)
Standby
Device Passed Device Failed
NOTES: A. See the recommended operating conditions for the value of VPPH. B. See the recommended operating conditions for the value of VPPL.
Figure 1. Algorithm-Selection Programming Flow Chart
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
9
SMJ28F010B 131072 BY 8-BIT FLASH MEMORY
SGMS738 - APRIL 1998
flow charts (continued)
Bus Operation Preprogram All Bytes = 00h ? Yes Address = 00h Initialize addresses VCC = 5 V 10%, VPP = 12 V 5% X=1 Write Set-Up-Erase Command Initialize pulse count Write-Erase Command Setup No Program All Bytes to 00h
Start
Command
Comments
Entire memory must = 00h before erasure Use fast-write programming algorithm
Standby
Wait for VPP to ramp to VPPH (see Note A)
Write
Wait = 10 ms X=X+1 Interactive Mode
Set-UpErase
Data = 20h
Write Erase-Verify Command
Write
Erase
Data = 20h
Wait = 6 s Increment Address No Read and Verify Byte Pass Fail X = 1000? Yes
Standby
Wait = 10 ms
Write
EraseVerify
Addr = Byte to verify; Data = A0h; ends the erase operation
Standby
No Last Address?
Wait = 6 s
Read
Yes Write Read Command Apply VPPL Apply VPPL Power Down
Read byte to verify erasure; compare output to FFh
Write
Read
Data = 00h; resets register for read operations Wait for VPP to ramp to VPPL (see Note B)
Device Passed
Device Failed
Standby
NOTES: A. Refer to the recommended operating conditions for the value of VPPH. B. Refer to the recommended operating conditions for the value of VPPL.
Figure 2. Flash-Erase Flow Chart
10
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
SMJ28F010B 131072 BY 8-BIT FLASH MEMORY
SGMS738 - APRIL 1998
flow charts (continued)
Start
Program All Devices to 00h
X=1
Give Erase Command to All Devices
Device # D = 1
Yes Mask Device #D
Is Device #D Erased ? No X = X+1
D = n ?
No D = D+1
Give Erase Command to All Unmasked Devices
Yes No
Are All Devices Erased ? Yes Give Read Command to All Devices
No X = 1000 ? Yes Give Read Command to All Devices
All Devices Pass
Finished With Errors
n = number of devices being erased.
Figure 3. Parallel-Erase Flow Chart
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
11
SMJ28F010B 131072 BY 8-BIT FLASH MEMORY
SGMS738 - APRIL 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.6 V to 7 V Supply voltage range, VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.6 V to 14 V Input voltage range (see Note 2): All inputs except A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.6 V to 7 V A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.6 V to 13.5 V Output voltage range (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.6 V to 7 V Output short-circuit current (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA Operating free-air temperature range during read / erase / program, TA . . . . . . . . . . . . . . . . . - 55 C to 125C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Maximum power dissipation, PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300C Junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to VSS. 2. The voltage on any input pin can undershoot to - 2 V for periods less than 20 ns. 3. The voltage on any output pin can overshoot to 7 V for periods less than 20 ns. 4. No more than one output can be shorted at a time, and the duration cannot exceed one second.
recommended operating conditions
MIN VCC VPP VIH VIL VID TA Supply voltage Supply voltage During write / read / flash erase During read only ( VPPL) During write / read / flash erase (VPPH) TTL CMOS TTL CMOS 4.5 0 11.4 2 VCC - 0.5 - 0.5 GND - 0.2 11.5 - 55 12 NOM 5 MAX 5.5 VCC + 2 12.6 VCC + 0.5 VCC + 0.5 0.8 GND + 0.2 13 125 UNIT V V V V V V C
High-level High level dc input voltage Low-level Low level dc input voltage Voltage level on A9 for algorithm-selection mode Operating free-air temperature
12
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
SMJ28F010B 131072 BY 8-BIT FLASH MEMORY
SGMS738 - APRIL 1998
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER VOH VOL IID II IO IPP1 IPP2 IPP3 IPP4 ICCS High-level High level output voltage Low-level Low level output voltage A9 algorithm-selection-mode current Input current (leakage) Output current (leakage) VPP supply current (read / standby) VPP supply current (during program pulse) VPP supply current (during flash erase) VPP supply current (during program / erase-verify) TTL-input level VCC supply current (standby) CMOS-input level VCC supply current (active read) VCC average supply current (active write) VCC average supply current (flash erase) VCC average supply current (program / erase-verify) All except A9 A9 TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, VCC = 4.5 V, IOL = 100 A VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VPP = VPPH, VPP = VPPL VPP = VPPH VPP = VPPH VPP = VPPH VCC = 5.5 V, E = VIH VCC = 5.5 V, E = VCC 0.2 V VCC = 5.5 V, E = VIL, f = 6 MHz, IOUT = 0 mA, G = VIH VCC = 5.5 V, E = VIL, Programming in progress VCC = 5.5 V, E = VIL, Erasure in progress VCC = 5.5 V, E = VIL, VPP = VPPH, Program / erase-verify in progress VPP = VPPH 2.5 IOH = - 2.5 mA IOH = - 100 A IOL = 5.8 mA A9 = VID max VI = 0 V to 5.5 V VI = 0 V to 13 V VO = 0 V to VCC Read mode MIN 2.4 VCC - 0.4 0.45 0.1 200* 1 200 10 200 10 30* 30* 5.0* 1 100 30 MAX UNIT V V A A A A mA mA mA mA A mA
ICC1 ICC2 ICC3 ICC4
10* 15*
mA mA
15*
mA V
VLKO VCC erase / write-lockout voltage * This parameter is not production tested.
capacitance over recommended range of supply voltage
PARAMETER Ci1 Co Ci2 Input capacitance Output capacitance VPP input capacitance TEST CONDITIONS VI = 0 V, TA = 25C, f = 1 MHz VO = 0 V, TA = 25C, f = 1 MHz VI = 0 V, TA = 25C, f = 1 MHz MIN MAX 10* 12* 12* UNIT pF pF pF
* This parameter is not production tested.
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
13
SMJ28F010B 131072 BY 8-BIT FLASH MEMORY
SGMS738 - APRIL 1998
switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Figure 6)
PARAMETER ta(A) ta(E) ten(G) tc(R) td(E) td(G) tdis(E) tdis(G) th(D) Access time from address, A0 - A16 Access time from chip enable, E Access time from output enable, G Cycle time, read Delay time, E low to low-Z output Delay time, G low to low-Z output Chip disable time to Hi-Z output Output disable time to Hi-Z output Hold time, data valid from address, E or G (see Note 5) CL = 100 pF, 1 Series 74 load, TTL load Input tr 10 ns, Input tf 10 ns TEST CONDITIONS ALTERNATE SYMBOL tAVQV tELQV tGLQV tAVAV tELQX tGLQX tEHQZ tGHQZ tAXQX tWHGL 120 0* 0* 0* 0* 0* 6 55* 30* '28F010B-12 MIN MAX 120 120 50 150 0* 0* 0* 0* 0* 6 55* 35* '28F010B-15 MIN MAX 150 150 55 200 0* 0* 0* 0* 0* 6 55* 45* '28F010B-20 MIN MAX 200 200 60 UNIT ns ns ns ns ns ns ns ns ns s
trec(W) Recovery time, W before read * This parameter is not production tested. NOTE 5: Whichever occurs first
14
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
SMJ28F010B 131072 BY 8-BIT FLASH MEMORY
SGMS738 - APRIL 1998
timing requirements-write/erase/program operations (see Figure 7 and Figure 8)
ALTERNATE SYMBOL tc(W) tc(W)PR tc(W)ER th(A) th(E) th(WHD) tsu(A) tsu(D) tsu(E) tsu(VPPEL) trec(W) trec(R) tw(W) tw(WH) tr(VPP) tf(VPP) Cycle time, write using W Cycle time, programming operation Cycle time, erase operation Hold time, address Hold time, E Hold time, data valid after W high Setup time, address Setup time, data Setup time, E before W Setup time, VPP to E low Recovery time, W before read Recovery time, read before W Pulse duration, W (see Note 6) Pulse duration, W high Rise time, VPP Fall time, VPP tAVAV tWHWH1 tWHWH2 tWLAX tWHEH tWHDX tAVWL tDVWH tELWL tVPEL tWHGL tGHWL tWLWH tWHWL tVPPR tVPPF '28F010B-12 MIN 120 10 9.5 60 0 10 0 50 20 1 6 0 60 20 1 1 10 NOM MAX '28F010B-15 MIN 150 10 9.5 60 0 10 0 50 20 1 6 0 60 20 1 1 10 NOM MAX '28F010B-20 MIN 200 10 9.5 60 0 10 0 50 20 1 6 0 60 20 1 1 10 NOM MAX
UNIT ns s ms ns ns ns ns ns ns s s s ns ns s s
NOTE 6: Rise / fall time 10 ns.
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
15
SMJ28F010B 131072 BY 8-BIT FLASH MEMORY
SGMS738 - APRIL 1998
timing requirements -- alternative E-controlled writes (see Figure 9)
ALTERNATE SYMBOL tc(W) tc(E)PR th(EA) th(ED) th(W) tsu(A) tsu(D) tsu(W) tsu(VPPEL) trec(E)R trec(E)W tw(E) tw(EH) Cycle time, write using E Cycle time, programming operation Hold time, address Hold time, data Hold time, W Setup time, address Setup time, data Setup time, W before E Setup time, VPP to E low Recovery time, write using E before read Recovery time, read before write using E Pulse duration, write using E Pulse duration, write, E high tAVAV tEHEH tELAX tEHDX tEHWH tAVEL tDVEH tWLEL tVPEL tEHGL tGHEL tELEH tEHEL '28F010B 12 '28F010B-12 MIN 120 10 80 10 0 0 50 0 1 6 0 70 20 MAX '28F010B 15 '28F010B-15 MIN 150 10 80 10 0 0 50 0 1 6 0 70 20 MAX '28F010B 20 '28F010B-20 MIN 200 10 80 10 0 0 50 0 1 6 0 70 20 MAX UNIT ns s ns ns ns ns ns ns s s s ns ns
PARAMETER MEASUREMENT INFORMATION
2.08 V RL = 800 Output Under Test CL = 100 pF (see Note A)
NOTE A: CL includes probe and fixture capacitance.
Figure 4. AC Test Output Load Circuit
2.4 V 0.45 V 2V 0.8 V 2V 0.8 V See Note A
NOTE A: The ac testing inputs are driven at 2.4 V for logic high and 0.45 V for logic low. Timing measurements are made at 2 V for logic high and 0.8 V for logic low on both inputs and outputs. Each device should have a 0.1-F ceramic capacitor connected between VCC and VSS as closely as possible to the device pins.
Figure 5. AC Test Input / Output Waveform
16
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
SMJ28F010B 131072 BY 8-BIT FLASH MEMORY
SGMS738 - APRIL 1998
PARAMETER MEASUREMENT INFORMATION
tc(R)
A0 - A16 ta(A) E
Address Valid
ta(E) G trec(W) W td(E) DQ0 - DQ7 Hi-Z td(G) ten(G)
tdis(E)
tdis(G) th(D) Ouput Valid Hi-Z
Figure 6. Read-Cycle Timing
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
17
SMJ28F010B 131072 BY 8-BIT FLASH MEMORY
SGMS738 - APRIL 1998
PARAMETER MEASUREMENT INFORMATION
Program Command Program Latch Verify Address and Data Programming Command
Power Up Set-UpProgram and Standby Command A0 - A16 tc(W) tsu(A) th(A) E tsu(E) th(E) G trec(R) W th(WHD) tw(W) tsu(D) DQ0 - DQ7 Hi-Z
Program Verification
Standby / Power Down
tc(W)
tc(W) th(A) tsu(A)
tc(R)
tsu(E) th(E) tc(W)PR tw(WH)
tsu(E) th(E)
tdis(E)
trec(W)
tdis(G)
th(WHD) tw(W) tsu(D) tw(W) tsu(D)
th(WHD)
th(D) ten(G) td(G)
Data In Data In = 40h 5V 0V VPP VPPH VPPL tr(VPP) tsu(VPPEL) Data In = C0h
td(E) ta(E)
Valid Data Out
VCC
tf(VPP)
Figure 7. Write-Cycle Timing
18
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
SMJ28F010B 131072 BY 8-BIT FLASH MEMORY
SGMS738 - APRIL 1998
PARAMETER MEASUREMENT INFORMATION
Power Up Set-UpErase and Standby Command A0 - A16 tc(W) tc(W) th(A) tsu(A) E tsu(E) th(E) G trec(R) W th(WHD) th(WHD) tw(W) tsu(D) DQ0 - DQ7 Hi-Z Data In = 20h Data In = 20h 5V VCC 0V tsu(VPPEL) VPPH VPP VPPL tr(VPP) tf(VPP) Data In = A0h td(E) ta(E) Valid Data Out tw(W) tsu(D) th(WHD) tw(W) tsu(D) tw(WH) tc(W)ER tsu(E) th(E) tsu(E) th(E) tdis(E) tc(R) EraseVerify Command
Erase Command
Erasing
Erase Standby / Verification Power Down
tc(W)
trec(W) tdis(G) th(D) ten(G) td(G)
Figure 8. Flash-Erase-Cycle Timing
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
19
SMJ28F010B 131072 BY 8-BIT FLASH MEMORY
SGMS738 - APRIL 1998
PARAMETER MEASUREMENT INFORMATION
Program Command Program Latch Verify Address and Data Programming Command
Power Up Set-UpProgram and Standby Command A0 - A16 tc(W) tsu(A) th(EA) W tsu(W) th(W) G trec(E)W
Program Verification
Standby / Power Down
tc(W)
tc(W) th(EA) tsu(A)
tc(R)
tsu(W) th(W) tc(E)PR tw(EH)
tsu(W) th(W)
tdis(G)
trec(E)R
tdis(E)
E th(ED) tw(E) tsu(D) DQ0 - DQ7 Hi-Z Data In Data In = 40h 5V 0V VPPH VPP VPPL tr(VPP) tf(VPP) tsu(VPPEL) Data In = C0h td(E) ta(E) Valid Data Out tsu(D) th(ED) tw(E) tw(E) tsu(D) th(D) th(ED) ten(G) td(G)
VCC
Figure 9. Write-Cycle (Alternative E-Controlled Writes) Timing
20
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
SMJ28F010B 131072 BY 8-BIT FLASH MEMORY
SGMS738 - APRIL 1998
MECHANICAL DATA
FE (R-CQCC-N**)
28 TERMINAL SHOWN A
LEADLESS CERAMIC CHIP CARRIER
17
13
NO. OF TERMINALS ** 18
A MIN 0.285 (7,24) 0.345 (8,76) 0.445 (11,30) MAX 0.295 (7,49) 0.355 (9,02) 0.455 (11,56) MIN 0.061 (1,55) 0.065 (1,65) 0.065 (1,65)
B MAX 0.073 (1,85) 0.079 (2,01) 0.079 (2,01) MIN 0.345 (8,76) 0.540 (13,72) 0.540 (13,72)
C MAX 0.365 (9,27) 0.560 (14,22) 0.560 (14,22)
18
12
28 32
C
26
4
27 0.045 (1,14) 0.035 (0,89)
1
3 0.025 (0,64) 0.015 (0,38) B
0.045 (1,14) 0.035 (0,89)
0.025 (0,64) 0.015 (0,38)
0.028 (0,71) 0.022 (0,56)
0.050 (1,27)
0.055 (1,40) 0.045 (1,14)
0.028 (0,71)
4040137 / B 03/95 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated.
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
21
SMJ28F010B 131072 BY 8-BIT FLASH MEMORY
SGMS738 - APRIL 1998
MECHANICAL DATA
JDD (R-CDIP-T32)
1.620 (41,15) 1.580 (40,13) 32 17
CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE
0.605 (15,37) 0.585 (14,86)
1 0.065 (1,65) 0.045 (1,14)
16
0.120 (3,05) 0.089 (2,26)
0.060 (1,52) 0.030 (0,76)
0.610 (15,49) 0.590 (14,99)
Seating Plane
0.100 (2,54)
0.021 (0,53) 0.015 (0,38)
0.175 (4,45) 0.125 (3,18)
0.014 (0,36) 0.008 (0,20) 4040280/B 03/96
NOTES: A. B. C. D.
All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals will be gold plated.
22
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current and complete. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ("Critical Applications"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI products in such applications requires the written approval of an appropriate TI officer. Questions concerning potential risk applications should be directed to TI through a local SC sales office. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TI warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.
Copyright (c) 1998, Texas Instruments Incorporated

▲Up To Search▲

Price & Availability of SMJ28F010B

	To Download SMJ28F010B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .